1. Technical Field
The present invention relates generally to finite state machines, and, in particular, to programmable finite state machines.
2. Background Art
In general, in the descriptions that follow, I will italicize the first occurrence of each special term of art which should be familiar to those skilled in the art of digital data processing systems, and, in particular, finite state machines (“FSMs”). In addition, when I first introduce a term that I believe to be new or that I will use in a context that I believe to be new, I will bold the term and provide the definition that I intend to apply to that term. From time to time, throughout this description, I will use the terms assert and negate when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively.
FSMs are the basis of many digital logic circuits. In general, a FSM is any logical entity designed to sequentially step, in a controlled manner, through a finite set of operating stages, called states. As shown in FIG. 1, a conventional, non-trivial FSM is comprised of three components:                A current state register (“CSR”), comprising m edge-triggered flip-flops, that latches an m-bit next state vector in response to the assertion of a clock signal (“Clock”), and thereafter provides as an output the latched next state vector as an m-bit current state vector;        A block of next state logic (“NSL”), consisting of combinational logic, that generates as an output the next state vector as a function of the current state vector and a multi-bit input vector; and        A block of output logic (“OL”), also consisting of combinational logic, that generates a selected one of n multi-bit output vectors as a function of the current state vector and, as appropriate, one or more of the various signals comprising the input vector.        
In operation, suitable start-up circuitry (not shown) generates a predetermined initial state vector, either directly or via the NSL, and forces the CSR to latch this vector. From the CSR, this initial state vector propagates to the NSL where, depending upon the instantaneous logical values of the various signals comprising the input vector, a selected next state vector will be dynamically generated. Upon the next assertion of the clock, the CSR will latch the then-current next state vector; any next state vectors generated by the NSL between clock assertions are simply ignored. Once latched, this next state vector becomes the current state vector. In each state, the OL will generate a respective output vector, each component signal of which will initiate/control one or more specific system operations. In a well defined FSM, this recursive process will repeat indefinitely, in synchronization with the clock, until the FSM reaches an end state, that is, a state from which there is no defined next state. To restart operation, the start-up circuit must be reactivated.
In the prior art, FSMs have been proposed in which a conventional programmable logic array (“PLA”) is used to implement either or both of the NSL and OL. A principle advantage of such an implementation is that the operating characteristics of the FSM can be easily and conveniently modified to adapt the FSM for use in diverse applications. One significant disadvantage of this technique, however, is that the structure of a PLA is fixed at the time of manufacturing and is thus not subject to subsequent reprogramming. Although it may be possible to use field-programmable PLAs or to substitute a conventional read/write memory (“RWM”) structure for a PLA, the re-programming operation is problematic, and I am aware of no proposed solutions.
A content addressable memory (“CAM”) is a digital circuit that performs the function of a fully associative memory. As shown in FIG. 2, a typical CAM is comprised of two components:                A compare register (“CR”), consisting of r edge-triggered flip-flops, that latches, in synchronization with a clock signal (“Clock”), an r-bit input vector to be matched; and        A compare array (“CA”), consisting of s match elements, each of which consists of r RWM cells that store a selected one of s r-bit compare vectors, and r-bit compare logic which generates as an output a respective bit of an s-bit match vector as a function of respective bits of the input vector and the stored compare vector.        
In a conventional binary CAM, each cell can store a selected one of two logical values: false or ‘0’; or true or ‘1’. In such an implementation, for a match to occur, the logical value of each bit of the input vector must exactly match the logical value of corresponding bit of the compare vector. I am aware of no prior art FSM implemented using CAMs.
In a ternary CAM (“TCAM”), each cell can store a selected one of three logical values: false or ‘0’; true or ‘1’; or don't care or ‘X’. In such an implementation, for a match to occur, the logical value of each bit of the input vector for which the logical value of the corresponding bit of the compare vector is not an ‘X’ must exactly match the logical value of corresponding bit of the compare vector; all bits of the input vector for which the corresponding bit of the compare vector is an ‘X’ are simply ignored when performing the match operation. Thus, the ‘X’ value functions as a per-bit mask enabling the TCAM to employ compare vectors containing wildcards. I am aware of no prior art FSM implemented using TCAMs.
In the rapidly growing telecommunications industry, protocols for the interchange of data tend to evolve quickly, with the result that hardware implementations frequently become obsolete before the cost thereof have been fully amortized. Although general purpose, programmable digital data processing systems can be used in such applications to provide field upgradeability, the processing power of such systems is usually underutilized, thus increasing unnecessarily the cost of such systems. But for the lack of field re-programmability, suitably programmed FSMs would provide a more cost effective solution for many of these applications. What is needed, therefore, is a field re-programmable FSM (“RFSM”). In particular, I submit that a more efficient apparatus and method is needed for re-programming a FSM.
In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers, and is not intended to imply or suggest that my invention requires identity in either function or structure in the several embodiments.